[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / nmsub_d.h

diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/nmsub_d.h
index 0c06f476d0ce8e0bcc1f0f0ead636d2cd4cea1bf..1e010c85bba1365983b995cbbd36a8390d72c268 100644 (file)
--- a/riscv/insns/nmsub_d.h
+++ b/riscv/insns/nmsub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;