[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / nor.h

diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h
index 5bb7e897f02332f3aad0ab60eef0be773867fd66..a3ba7d154c0a546956333e34533dfb4c227e1cda 100644 (file)
--- a/riscv/insns/nor.h
+++ b/riscv/insns/nor.h
@@ -1 +1 @@
-RC = ~(RA | RB);
+RDR = ~(RS1 | RS2);