Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / ori.h

diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 695a56ba0ecec63e8c7528c1708b038c4c113394..6403c39b5b476fa98948a6aa44dbbbdb1b430a74 100644 (file)
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RD = insn.i_imm() | RS1;
+WRITE_RD(insn.i_imm() | RS1);