[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / rdtime.h

diff --git a/riscv/insns/rdtime.h b/riscv/insns/rdtime.h
index 96f2a74050d7b3b4326f95f2a0327f748ff0dd61..9b966a683554407e2ddb44448101f2721e63e72e 100644 (file)
--- a/riscv/insns/rdtime.h
+++ b/riscv/insns/rdtime.h
@@ -1 +1 @@
-throw trap_illegal_instruction;
+RD = cycle;