[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / rem.h

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index dfece4377300350c02b537ded1279db759b6edce..9192428e37519adac62cd422e28490aa20a7f4c1 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,2 +1,2 @@
 require64;
-RC = sreg_t(RA) % sreg_t(RB);
+RDR = sreg_t(RS1) % sreg_t(RS2);