[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / rem.h

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 1bc94f2556c165ebe7d687e031433808012ab6d5..ac82a56f4179219a30354d11a9e4531ee45569d4 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,5 +1,6 @@
-require64;
-if(RS2 == 0 || (sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1))
+if(RS2 == 0)
+  RD = RS1;
+else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
   RD = 0;
 else
-  RD = sreg_t(RS1) % sreg_t(RS2);
+  RD = sext_xprlen(sext_xprlen(RS1) % sext_xprlen(RS2));