Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / rem.h

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 8094b5bba1715b3c59db12b7e99073f2644d7069..fa98ac6893f8a2919c3a974a916889cc8757427b 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,8 +1,8 @@
 sreg_t lhs = sext_xprlen(RS1);
 sreg_t rhs = sext_xprlen(RS2);
 if(rhs == 0)
-  RD = lhs;
+  WRITE_RD(lhs);
 else if(lhs == INT64_MIN && rhs == -1)
-  RD = 0;
+  WRITE_RD(0);
 else
-  RD = sext_xprlen(lhs % rhs);
+  WRITE_RD(sext_xprlen(lhs % rhs));