[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / remu.h

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index e8ee6b1a3ee711c1b4f3268fa3237ea2fd885e90..2f40aaa7d6e018c5a046a423633dbc09d4d8d382 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA % RB;
+RDR = RS1 % RS2;