[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / remu.h

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index d028488e9d059cc7baa0ee81b97223cf39ac19a9..c698aca2fefadae41f339b9d947e4e47b5ee5c4c 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,4 @@
-RC = sext32(uint32_t(RA) % uint32_t(RB));
-
+if(RS2 == 0)
+  RD = RS1;
+else
+  RD = sext_xprlen(zext_xprlen(RS1) % zext_xprlen(RS2));