[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / remw.h

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 1bb3051d9692d4d3d7d70fd4bf508cd06225ab0c..93c38588efb48cbd0411030e7c1ac93a5b2f2dd2 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,2 +1,7 @@
-RC = sext32(int32_t(RA) % int32_t(RB));
-
+require_xpr64;
+if(RS2 == 0)
+  RD = RS1;
+else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
+  RD = 0;
+else
+  RD = sext32(int32_t(RS1) % int32_t(RS2));