[sim] fixed some compiler warnings

[riscv-isa-sim.git] / riscv / insns / remw.h

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 0e68dc6e3b524e1830b4ec800ea8b13505135871..eb23ef1c4ac90a932f2a1d7aa1153b264fcae1f0 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,4 +1,4 @@
-if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
+if(int32_t(RS2) == 0 || (int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1))
   RD = 0;
 else
   RD = sext32(int32_t(RS1) % int32_t(RS2));