[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / s_d.h

diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h
index d1c80377b6cebfd04e0372a5403410ebb7ef1c21..4c9c466c653cd47c1766374c54c0b7ec5f7cf2e4 100644 (file)
--- a/riscv/insns/s_d.h
+++ b/riscv/insns/s_d.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint64(RB+SIMM, FRA);
+mmu.store_uint64(RS1+SIMM, FRS2);