[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sb.h

diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index 5a2110fccc4fe10e2595366674976d7e82d994f6..af5bd10240fb63d249915809bb9930b62b0fbf0a 100644 (file)
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(RS1+SIMM, RS2);
+mmu.store_uint8(RS1+BIMM, RS2);