Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / sc_d.h

diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index 9ad962c6bd810736e1baf2885eba19da89a3d18d..3b4824445c77a6a148fde9a231ba5d52852e8b3c 100644 (file)
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -2,7 +2,7 @@ require_xpr64;
 if (RS1 == p->get_state()->load_reservation)
 {
   MMU.store_uint64(RS1, RS2);
-  RD = 0;
+  WRITE_RD(0);
 }
 else
-  RD = 1;
+  WRITE_RD(1);