[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sd.h

diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 587df8df47ce21f621d1bb2203e85fb67e58550d..2009149a4bc8d654b203e4e378bbd070b5724750 100644 (file)
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
-require64;
-mmu.store_uint64(RS1+SIMM, RS2);
+require_xpr64;
+mmu.store_uint64(RS1+BIMM, RS2);