[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sgninjn_d.h

diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/sgninjn_d.h
index c526735a3806161e1ad2339de3a46e4d50738ff7..90c7ae9bd9d2fae7744b274eb09e88aa1b13bd62 100644 (file)
--- a/riscv/insns/sgninjn_d.h
+++ b/riscv/insns/sgninjn_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (FRA &~ INT64_MIN) | ((~FRB) & INT64_MIN);
+FRDR = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);