[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sgninjn_s.h

diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/sgninjn_s.h
index 80dd7e875396276a6581b30759c4a9790c94f2b6..7be7b46623cacf406680306f65597947d84b3dae 100644 (file)
--- a/riscv/insns/sgninjn_s.h
+++ b/riscv/insns/sgninjn_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (FRA &~ (uint32_t)INT32_MIN) | ((~FRB) & (uint32_t)INT32_MIN);
+FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);