[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sll.h

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 7e81e6b68b45a278591a6bd73ebb0e5c8613b3de..59da49de6f92a6abcb1e03f76088fd6351f7207b 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1,2 +1,2 @@
 require64;
-RC = RB << (RA & 0x3F);
+RDR = RS2 << (RS1 & 0x3F);