[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sll.h

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 7e81e6b68b45a278591a6bd73ebb0e5c8613b3de..86eb96682ca3a1818f29ed18310415a9647fcaf1 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1,2 +1 @@
-require64;
-RC = RB << (RA & 0x3F);
+RD = sext_xprlen(RS1 << (RS2 & (xprlen-1)));