Implement RVC draft

[riscv-isa-sim.git] / riscv / insns / slli.h

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 151d97023f8be409106d7679606ec87efbd9eb5b..dfe7168193f9dac8848aa32ce5173b9cbf9caa8e 100644 (file)
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,8 +1,3 @@
-if(xpr64)
-  RD = RS1 << SHAMT;
-else
-{
-  if(SHAMT & 0x20)
-    throw trap_illegal_instruction();
-  RD = sext32(RS1 << SHAMT);
-}
+if (SHAMT >= xlen)
+  throw trap_illegal_instruction();
+WRITE_RD(sext_xlen(RS1 << SHAMT));