Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / slliw.h

diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 8ef4ae782fb2b2f67df810ad64437fbbd5af8a1a..fdb51be695fb267cf9a17e41a8116e82581e5a89 100644 (file)
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 << SHAMT);
+WRITE_RD(sext32(RS1 << SHAMT));