[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sllw.h

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index f694a2ff3ce019a24881f8d528c200f08107ecfe..3d96b0fb21ce02a7dead68d78707527b8222cc4c 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1 @@
-RC = sext32(RB << (RA & 0x1F));
+RDR = sext32(RS2 << (RS1 & 0x1F));