[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sllw.h

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 67e6809cafd3169a866da9d38e1eba56de6c174a..f3356d89f826b8c0d2a920e08d04be14b831fb13 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1,2 @@
-RC = sext32(RB << SHAMT);
+require_xpr64;
+RD = sext32(RS1 << (RS2 & 0x1F));