Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / slt.h

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 5c50534a97b13500dc376a7f86ad14c1115b16c0..dd6e58ec8ea7e7e44a68c8373f7fbc17a3b17063 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));
+WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)));