[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sra.h

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index 6dfde0f49decdea983043473f1a1a4a4044c16e2..7102da0c0ff46540004ea27aaf250e6c5c045a5d 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1,2 +1 @@
-require64;
-RDR = sreg_t(RS2) >> (RS1 & 0x3F);
+RD = sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1)));