[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sra.h

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index c2decb99b2e64148540c9a12c17f6021b433721c..7102da0c0ff46540004ea27aaf250e6c5c045a5d 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1 @@
-RC = sext32(sreg_t(RB) >> SHAMT);
+RD = sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1)));