[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / srai.h

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index 18fc55bf69ae64fa61ecdfee5b0dbfaeb1e03b85..bb17d2767c6533d3be35c6069d802b53af7fb22b 100644 (file)
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -4,5 +4,5 @@ else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction;
-  RD = sext32(sreg_t(RS1) >> SHAMT);
+  RD = sext32(int32_t(RS1) >> SHAMT);
 }