[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / srai.h

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index b2026bb5c9486899dbb41b1e91990e9f53fb73c1..bb17d2767c6533d3be35c6069d802b53af7fb22b 100644 (file)
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,2 +1,8 @@
-require64;
-RDI = sreg_t(RS1) >> SHAMT;
+if(xpr64)
+  RD = sreg_t(RS1) >> SHAMT;
+else
+{
+  if(SHAMT & 0x20)
+    throw trap_illegal_instruction;
+  RD = sext32(int32_t(RS1) >> SHAMT);
+}