[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sraiw.h

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 0831b1428d00d75caf01b371b02d7c1582b19a6a..4c5673007d1dcd9e4d169136c7df2ed8a5041908 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1 +1,2 @@
-RDI = sext32(sreg_t(RS1) >> SHAMTW);
+require_xpr64;
+RD = sext32(int32_t(RS1) >> SHAMTW);