[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sraw.h

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index 8e9aa8825f14dd27ffccb400ad539282fa940ea0..111f6328aeff8b4d4911796246ec7278bc69f9bb 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1 +1 @@
-RC = sext32(sreg_t(RB) >> (RA & 0x1F));
+RDR = sext32(sreg_t(RS2) >> (RS1 & 0x1F));