[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / sraw.h

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index 8e9aa8825f14dd27ffccb400ad539282fa940ea0..d1783741bbe19fff75e4fcf68d52b527b04a608c 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1 +1,2 @@
-RC = sext32(sreg_t(RB) >> (RA & 0x1F));
+require_xpr64;
+RD = sext32(int32_t(RS1) >> (RS2 & 0x1F));