Implement mstatus.TW, mstatus.TVM, and mstatus.TSR

[riscv-isa-sim.git] / riscv / insns / sret.h

diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h
index 442b00b3545090e89af3fcd1e870a49bf3252ab0..e4d05023b6d4c83ab80c09157a4ec2fa4e4c30a3 100644 (file)
--- a/riscv/insns/sret.h
+++ b/riscv/insns/sret.h
@@ -1,5 +1,9 @@
-require_supervisor;
-p->set_pcr(CSR_STATUS, ((p->get_state()->sr & ~(SR_S | SR_EI)) |
-                       ((p->get_state()->sr & SR_PS) ? SR_S : 0)) |
-                       ((p->get_state()->sr & SR_PEI) ? SR_EI : 0));
-set_pc(p->get_state()->epc);
+require_privilege(get_field(STATE.mstatus, MSTATUS_TSR) ? PRV_M : PRV_S);
+set_pc_and_serialize(p->get_state()->sepc);
+reg_t s = STATE.mstatus;
+reg_t prev_prv = get_field(s, MSTATUS_SPP);
+s = set_field(s, MSTATUS_UIE << prev_prv, get_field(s, MSTATUS_SPIE));
+s = set_field(s, MSTATUS_SPIE, 1);
+s = set_field(s, MSTATUS_SPP, PRV_U);
+p->set_privilege(prev_prv);
+p->set_csr(CSR_MSTATUS, s);