[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / srli.h

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index d7bc2b418490f3e847758c1ce252e3d9cfbd6bf7..29a97a2e51254d0aced63050cbf5e1dc162048a4 100644 (file)
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,2 @@
 require64;
-RA = RB >> SHAMT;
+RDI = RS1 >> SHAMT;