[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / srli.h

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index d7bc2b418490f3e847758c1ce252e3d9cfbd6bf7..5378fd1e57118756fbf8574ff5ddeeeb5c7ed8d2 100644 (file)
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,8 @@
-require64;
-RA = RB >> SHAMT;
+if(xpr64)
+  RD = RS1 >> SHAMT;
+else
+{
+  if(SHAMT & 0x20)
+    throw trap_illegal_instruction;
+  RD = sext32((uint32_t)RS1 >> SHAMT);
+}