[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / srliw.h

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 5513a5a403402e20db90e026ff236a5c837f223f..c400507570fd3adc08fbd69191b5101b7a43f2b4 100644 (file)
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1 +1,2 @@
-RDI = sext32((uint32_t)RS1 >> SHAMTW);
+require_xpr64;
+RD = sext32((uint32_t)RS1 >> SHAMTW);