[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / srlw.h

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index c523b59dbe1bc55a3d0cd367ce0db3dc3ad8cc97..2d9de89f968653864bd94cb8551e526a6dc1f958 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1 @@
-RC = sext32((uint32_t)RB >> (RA & 0x1F));
+RDR = sext32((uint32_t)RS2 >> (RS1 & 0x1F));