[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / srlw.h

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index c523b59dbe1bc55a3d0cd367ce0db3dc3ad8cc97..b206f7c86a24951364c0d5792f1bd191854ab9e1 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1,2 @@
-RC = sext32((uint32_t)RB >> (RA & 0x1F));
+require_xpr64;
+RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));