[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sub.h

diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index e7ac407639435d582f7aa08ad9b08a27e0d19e54..005b66f4c3d9baae2749525b3e8d6338d696551c 100644 (file)
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA - RB;
+RDR = RS1 - RS2;