[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sub_s.h

diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h
index fd83da031b63a2f38862cbde04de2a598b61fd62..e28f042dbfc5218020b7ce6ed92213859426e92b 100644 (file)
--- a/riscv/insns/sub_s.h
+++ b/riscv/insns/sub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_sub(FRA, FRB);
+FRDR = f32_sub(FRS1, FRS2);
 set_fp_exceptions;