[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / subw.h

diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
index 958cc5d7a67b345d755c7a2615b0147ae35f6822..28db33481c28eebdd134eb103444432bac483ceb 100644 (file)
--- a/riscv/insns/subw.h
+++ b/riscv/insns/subw.h
@@ -1,2 +1,3 @@
+require_xpr64;
 RD = sext32(RS1 - RS2);