[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / trunc_w_d.h

diff --git a/riscv/insns/trunc_w_d.h b/riscv/insns/trunc_w_d.h
index b91640a3ac59c91f72fdcaa5919bf72f38660782..2fea3dcadf656b075e21a50ad0071ffcc81065b5 100644 (file)
--- a/riscv/insns/trunc_w_d.h
+++ b/riscv/insns/trunc_w_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_i32_r_minMag(FRA,true);
+FRDR = f64_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;