[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / trunc_w_s.h

diff --git a/riscv/insns/trunc_w_s.h b/riscv/insns/trunc_w_s.h
index 73974d1f28362ddf457913d35ebebde7d2a0077d..e70f9c4795c1009289198b111965db50351ebaf4 100644 (file)
--- a/riscv/insns/trunc_w_s.h
+++ b/riscv/insns/trunc_w_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_i32_r_minMag(FRA,true);
+FRDR = f32_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;