[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / truncu_l_d.h

diff --git a/riscv/insns/truncu_l_d.h b/riscv/insns/truncu_l_d.h
index 0fad400c10cd33dedfbfb4a04aef78490ba40b74..e71957bfdf4b9b584edd67f29488b55768129823 100644 (file)
--- a/riscv/insns/truncu_l_d.h
+++ b/riscv/insns/truncu_l_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_i64_r_minMag(FRA,true);
+FRDR = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;