[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / vf.h

diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..777964544e3c1cd9f978ae8a3be38ec50d21de53 100644 (file)
--- a/riscv/insns/vf.h
+++ b/riscv/insns/vf.h
@@ -0,0 +1,8 @@
+require_vector;
+for (int i=0; i<VL; i++)
+{
+  uts[i]->pc = RS1+SIMM;
+  uts[i]->utmode = true;
+  while (uts[i]->utmode)
+    uts[i]->step(1, false); // XXX
+}