#include <string>
#include <vector>
#include <algorithm>
+#include <math.h>
DECLARE_TRAP(-1, interactive)
throw trap_interactive();
processor_t *p = get_core(args[0]);
- return p->state.pc;
+ return p->get_state()->pc;
}
void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args)
if (r >= NXPR)
throw trap_interactive();
- return p->state.XPR[r];
+ return p->get_state()->XPR[r];
}
freg_t sim_t::get_freg(const std::vector<std::string>& args)
if (r >= NFPR)
throw trap_interactive();
- return p->state.FPR[r];
+ return p->get_state()->FPR[r];
}
void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args)
processor_t *p = get_core(args[0]);
for (int r = 0; r < NXPR; ++r) {
- fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->state.XPR[r]);
+ fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->get_state()->XPR[r]);
if ((r + 1) % 4 == 0)
fprintf(stderr, "\n");
}
void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args)
{
- fprintf(stderr, "0x%016" PRIx64 "\n", get_freg(args).v);
+ freg_t r = get_freg(args);
+ fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]);
}
void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
- fprintf(stderr, "%g\n",f.s);
+ fprintf(stderr, "%g\n", isBoxedF32(f.r) ? (double)f.s : NAN);
}
void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
- fprintf(stderr, "%g\n",f.d);
+ fprintf(stderr, "%g\n", isBoxedF64(f.r) ? f.d : NAN);
}
reg_t sim_t::get_mem(const std::vector<std::string>& args)