Reset to "success" instead of "error."

[riscv-isa-sim.git] / riscv / jtag_dtm.cc

diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc
index cd3f3ee996a94a12ac9861d320ce62b43ff7338d..3a0e8d254096903e94ba0f1d828e6cf76d54dbbe 100644 (file)
--- a/riscv/jtag_dtm.cc
+++ b/riscv/jtag_dtm.cc
@@ -41,7 +41,7 @@ jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) :
   dm(dm),
   _tck(false), _tms(false), _tdi(false), _tdo(false),
   dtmcontrol((abits << DTM_DTMCS_ABITS_OFFSET) | 1),
-  dmi(DMI_OP_STATUS_FAILED << DTM_DMI_OP_OFFSET),
+  dmi(DMI_OP_STATUS_SUCCESS << DTM_DMI_OP_OFFSET),
   _state(TEST_LOGIC_RESET)
 {
 }