Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / jtag_dtm.h

diff --git a/riscv/jtag_dtm.h b/riscv/jtag_dtm.h
index 6d89c042aeeecd51173c8045dd63ab7db9158174..063e3f40b3416271255699b9fd2dfee0c781f507 100644 (file)
--- a/riscv/jtag_dtm.h
+++ b/riscv/jtag_dtm.h
@@ -36,6 +36,8 @@ class jtag_dtm_t
 
     bool tdo() const { return _tdo; }
 
+    jtag_state_t state() const { return _state; }
+
   private:
     debug_module_t *dm;
     bool _tck, _tms, _tdi, _tdo;
@@ -48,9 +50,9 @@ class jtag_dtm_t
     // constructor.
     const unsigned abits = 6;
     uint32_t dtmcontrol;
-    uint64_t dbus;
+    uint64_t dmi;
 
-    jtag_state_t state;
+    jtag_state_t _state;
 
     void capture_dr();
     void update_dr();