#include "sim.h"
#include "processor.h"
-mmu_t::mmu_t(char* _mem, size_t _memsz)
- : mem(_mem), memsz(_memsz), proc(NULL)
+mmu_t::mmu_t(sim_t* sim, processor_t* proc)
+ : sim(sim), proc(proc)
{
flush_tlb();
}
flush_icache();
}
-void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
+reg_t mmu_t::translate(reg_t addr, access_type type)
{
- reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
- reg_t expected_tag = addr >> PGSHIFT;
-
- reg_t pte = 0;
- reg_t mstatus = proc ? proc->state.mstatus : 0;
-
- bool vm_disabled = get_field(mstatus, MSTATUS_VM) == VM_MBARE;
- bool mode_m = get_field(mstatus, MSTATUS_PRV) == PRV_M;
- bool mode_s = get_field(mstatus, MSTATUS_PRV) == PRV_S;
- bool mprv_m = get_field(mstatus, MSTATUS_MPRV) == PRV_M;
- bool mprv_s = get_field(mstatus, MSTATUS_MPRV) == PRV_S;
-
- if (vm_disabled || (mode_m && (mprv_m || fetch))) {
- // virtual memory is disabled. merely check legality of physical address.
- if (addr < memsz) {
- // produce a fake PTE for the TLB's benefit.
- pte = PTE_V | PTE_UX | PTE_SX | ((addr >> PGSHIFT) << PGSHIFT);
- if (vm_disabled || !(mode_m && !mprv_m))
- pte |= PTE_UR | PTE_SR | PTE_UW | PTE_SW;
- }
- } else {
- pte = walk(addr);
+ if (!proc)
+ return addr;
+
+ reg_t mode = proc->state.prv;
+ bool pum = false;
+ if (type != FETCH) {
+ if (get_field(proc->state.mstatus, MSTATUS_MPRV))
+ mode = get_field(proc->state.mstatus, MSTATUS_MPP);
+ pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
}
+ if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
+ mode = PRV_M;
- reg_t pte_perm = pte & PTE_PERM;
- if (mode_s || (mode_m && mprv_s && !fetch))
- pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
- pte_perm |= pte & PTE_V;
+ if (mode == PRV_M) {
+ reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
+ return addr & msb_mask;
+ }
+ return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1));
+}
- reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_V;
- if(unlikely((pte_perm & perm) != perm))
- {
- if (fetch)
+const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
+{
+ reg_t paddr = translate(addr, FETCH);
+ if (sim->addr_is_mem(paddr)) {
+ refill_tlb(addr, paddr, FETCH);
+ return (const uint16_t*)sim->addr_to_mem(paddr);
+ } else {
+ if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
throw trap_instruction_access_fault(addr);
- if (store)
- throw trap_store_access_fault(addr);
- throw trap_load_access_fault(addr);
+ return &fetch_temp;
}
+}
- reg_t pgoff = addr & (PGSIZE-1);
- reg_t pgbase = pte >> PGSHIFT << PGSHIFT;
- reg_t paddr = pgbase + pgoff;
-
- if (unlikely(tracer.interested_in_range(pgbase, pgbase + PGSIZE, store, fetch)))
- tracer.trace(paddr, bytes, store, fetch);
- else
- {
- tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
- tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
- tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
- tlb_data[idx] = mem + pgbase - (addr & ~(PGSIZE-1));
+void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
+{
+ reg_t paddr = translate(addr, LOAD);
+ if (sim->addr_is_mem(paddr)) {
+ memcpy(bytes, sim->addr_to_mem(paddr), len);
+ if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
+ tracer.trace(paddr, len, LOAD);
+ else
+ refill_tlb(addr, paddr, LOAD);
+ } else if (!sim->mmio_load(paddr, len, bytes)) {
+ throw trap_load_access_fault(addr);
}
+}
- return mem + paddr;
+void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
+{
+ reg_t paddr = translate(addr, STORE);
+ if (sim->addr_is_mem(paddr)) {
+ memcpy(sim->addr_to_mem(paddr), bytes, len);
+ if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
+ tracer.trace(paddr, len, STORE);
+ else
+ refill_tlb(addr, paddr, STORE);
+ } else if (!sim->mmio_store(paddr, len, bytes)) {
+ throw trap_store_access_fault(addr);
+ }
}
-pte_t mmu_t::walk(reg_t addr)
+void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
{
- reg_t msb_mask = -(reg_t(1) << (VA_BITS-1));
- if ((addr & msb_mask) != 0 && (addr & msb_mask) != msb_mask)
- return 0; // address isn't properly sign-extended
+ reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
+ reg_t expected_tag = vaddr >> PGSHIFT;
- reg_t base = proc->get_state()->sptbr;
- reg_t ptd;
+ if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
+ if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
+ if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
- int ptshift = (LEVELS-1)*PTIDXBITS;
- for (reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS) {
- reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
+ if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
+ else if (type == STORE) tlb_store_tag[idx] = expected_tag;
+ else tlb_load_tag[idx] = expected_tag;
- // check that physical address of PTE is legal
- reg_t pte_addr = base + idx*sizeof(pte_t);
- if (pte_addr >= memsz)
- return 0;
+ tlb_data[idx] = sim->addr_to_mem(paddr) - vaddr;
+}
- ptd = *(pte_t*)(mem+pte_addr);
+reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
+{
+ int levels, ptidxbits, ptesize;
+ switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
+ {
+ case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
+ case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
+ case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
+ default: abort();
+ }
- if (!(ptd & PTE_V)) { // invalid mapping
- return 0;
- } else if (ptd & PTE_T) { // next level of page table
- base = (ptd >> PGSHIFT) << PGSHIFT;
+ // verify bits xlen-1:va_bits-1 are all equal
+ int va_bits = PGSHIFT + levels * ptidxbits;
+ reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
+ reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
+ if (masked_msbs != 0 && masked_msbs != mask)
+ return -1;
+
+ reg_t base = proc->get_state()->sptbr << PGSHIFT;
+ int ptshift = (levels - 1) * ptidxbits;
+ for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
+ reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
+
+ // check that physical address of PTE is legal
+ reg_t pte_addr = base + idx * ptesize;
+ if (!sim->addr_is_mem(pte_addr))
+ break;
+
+ void* ppte = sim->addr_to_mem(pte_addr);
+ reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
+ reg_t ppn = pte >> PTE_PPN_SHIFT;
+
+ if (PTE_TABLE(pte)) { // next level of page table
+ base = ppn << PGSHIFT;
+ } else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
+ break;
+ } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
+ break;
} else {
- // we've found the PTE.
+ // set referenced and possibly dirty bits.
+ *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
// for superpage mappings, make a fake leaf PTE for the TLB's benefit.
reg_t vpn = addr >> PGSHIFT;
- ptd |= (vpn & ((1<<(ptshift))-1)) << PGSHIFT;
-
- // check that physical address is legal
- if (((ptd >> PGSHIFT) << PGSHIFT) >= memsz)
- return 0;
-
- return ptd;
+ return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
}
}
- return 0;
+
+ return -1;
}
void mmu_t::register_memtracer(memtracer_t* t)
projects / riscv-isa-sim.git / blobdiff