Fix 2 trigger corner cases. (#229)

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index e954e5a51d6f322596398f1e0e4e936cecc4de71..021f587eaac5ac23c42ae0fa8b88c93c4ca27ec5 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 
 #include "mmu.h"
-#include "sim.h"
+#include "simif.h"
 #include "processor.h"
 
 mmu_t::mmu_t(simif_t* sim, processor_t* proc)
@@ -12,6 +12,7 @@ mmu_t::mmu_t(simif_t* sim, processor_t* proc)
   matched_trigger(NULL)
 {
   flush_tlb();
+  yield_load_reservation();
 }
 
 mmu_t::~mmu_t()