add load-reserved/store-conditional instructions

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index e95e5f9fc4734065b57bd65d44ea03a33045d2c8..3cdb21dc2b91aa84c17af1ae2d0b89c277c1ee8b 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -6,9 +6,9 @@
 
 mmu_t::mmu_t(char* _mem, size_t _memsz)
  : mem(_mem), memsz(_memsz), badvaddr(0),
-   ptbr(0), sr(SR_S)
+   ptbr(0)
 {
-  flush_tlb();
+  set_sr(SR_S);
 }
 
 mmu_t::~mmu_t()
@@ -29,6 +29,13 @@ void mmu_t::flush_tlb()
   flush_icache();
 }
 
+void mmu_t::set_sr(uint32_t _sr)
+{
+  sr = _sr;
+  flush_tlb();
+  yield_load_reservation();
+}
+
 reg_t mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
 {
   reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;